Reversible Logic Circuit Based Twiddle Factor Generation

An efficient hardware implementation of FFT algorithm become essential one in signal analysis domain, more specifically the twiddle factor calculation in FFT computation plays important role in the speed and efficiency of the complete process. World of computation needs the fast and efficient tools to match the need of present scenario, even though there are many methods proposed the Reversible Logic design became the promising area for improvement of speed and reduces the power consumption to a larger extent. In this paper a reversible logic based implementation of twiddle factor generation is proposed.